//------------------------------------------------------------------------------
// File       : gig_ethernet_pcs_pma_0_resets.v
// Author     : Xilinx Inc.
//------------------------------------------------------------------------------
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//------------------------------------------------------------------------------
// Description: This module holds the resets for the PCS/PMA core


`timescale 1 ps/1 ps


//------------------------------------------------------------------------------
// The module declaration for the example design
//------------------------------------------------------------------------------

module gig_ethernet_pcs_pma_0_resets
   (
    input        reset,                    // Asynchronous reset for entire core.
    input        independent_clock_bufg,   // System clock
    output       pma_reset                 // Synchronous transcevier PMA reset
   );

   (* ASYNC_REG = "TRUE" *)
   reg   [3:0]  pma_reset_pipe;           // flip-flop pipeline for reset duration stretch

   

   //---------------------------------------------------------------------------
   // Transceiver PMA reset circuitry
   //---------------------------------------------------------------------------

   always@(posedge independent_clock_bufg or posedge reset)
      if (reset == 1'b1)
         pma_reset_pipe <= 4'b1111;
      else
         pma_reset_pipe <= {pma_reset_pipe[2:0], reset};

   assign pma_reset = pma_reset_pipe[3] ;

endmodule // gig_ethernet_pcs_pma_0_resets
